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موسسه‌ی آموزش عالی ارومی از بدو تاسیس، همواره کیفیت بالای آموزش و کار پژوهشی را در صدر اولویت‌های خود قرار داده‌ و دانشجویان را به حفظ معیارهای بالا در انجام کارهای پژوهشی تشویق کرده‌است. نتیجه‌ی این روش، انتشار و ارائه‌ی ده‌ها عنوان مقاله در نشریات و کنفرانس‌های معتبر داخلی و خارجی توسط دانشجویان این موسسه در سال‌های اخیر است.
 
مقالات منتشر‌شده در مجلات ISI
  1. Sarang Kazeminia, Sobhan Sofi Mowloodi, Khayrollah Hadidi, “A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump”, Journal of Circuits System and Computers, September 2014;  Vol.24, No.1, January 2015. DOI: 10.1142/S0218126615500012.

  2. Sarang Kazeminia, Obalit Shino, Ehsan Haghigh, Khayrollah Hadidi, “Speed Enhancement and Kickback noise reduction in single-stage latched comparator improved for high-speed and low-noise analogue-to-digital converters”, International Journal of Electronics Letters, Taylor & Francis, 05 Oct 2015, DOI: 10.1080/21681724.2015.1092592, ISSN: 2168-1724.

  3. Ali Baradaran Rezaeii, Obalit Shino and Tohid Moradi, “Low-Kickback-Noise Preamplifier-Latched Comparators Designed for High-Speed & Accurate ADCs”; Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 4 (2014), 312 – 320.

  4. Ali Baradaran Rezaeii and Obalit Shino, “An Ultra-High-Speed High-Resolution Low-Offset Low-Power Voltage Comparator with a Reliable Offset Cancellation Method for High-Performance Applications in 0.18µm CMOS Technology”; Analog integrated circuits and signal processing, Springer 2015.

  5. Mahdavi, Sina & Poreh, Maryam & Alizadeh, Leyla & Moradkhani, Baran & Ebrahimi, Rezvan. (2017). A 1.25GS/s 12bit and 2.27mW Digital to Analog Converter (DAC) with 70.22 SNDR Based on New Hybrid R-C Procedure in 180nm CMOS. international journal of microelectronics and computer science. 8. 127-132.

  6. Mahdavi, Sina & Soltani, Arefeh & Poreh, Maryam & Moradi, Tohid. (2016). An Ultra High speed Low power Low settling time error and wide dynamic range voltage Continuous-time Common-Mode Feedback Circuit in 0.18µm CMOS. Bulletin de la Societe Royale des Sciences de Liege.

  7. Mahdavi, Sina & Soltani, A & Jafarzadeh, M & Moradi Khanshan, T. (2016). A Novel Method to Design Variable Gain Amplifier. Journal of Applied and Fundamental Sciences. 8. 10.4314/jfas.v8i2s147.

  8. Mahdavi, Sina & Noruzpur, Faeze & Alizadeh, Leyla & Jalilzadeh, Maryam & judy, Farahnaz. (2017). A 0.88nS Settling Time 115μV Settling Error with 68.18dB SNDR Continuous-time Common-Mode Feedback (CMFB) Circuit in 180nm CMOS Technology. International Journal of Mechatronics, Electrical and Computer Technology (IJMEC).

  9. Mahdavi, Sina & Noruzpur, Faeze & Ghadimi, Esmail & Moradi Khanshan, Tohid. (2017). A Novel High-Swing High-Speed With 187µW Power Consumption Common-Mode Feedback Block (CMFB) Based on Rail-to-Rail Technique. International Journal of Microelectronics and Computer Science (IJMCS).

  10. Sarang Kazeminia and Khayrollah Hadidi, “A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs,” Integration, the VLSI Journal. 61. 10.1016/j.vlsi.2017.11.005 (2017).

  11. Sarang Kazeminia, Roozbeh Abdollahi and Arash Hejazi, “A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability,” Analog Integrated Circuits and Signal Processing. 94. 10.1007/s10470-018-1109-5 (2018).

  12. Babazadeh, A., Moradi Khanshan, T. & Esmaili, A., “An improved adaptive DFE structure based on ISI detection,” Analog Integr Circ Sig Process (2019). https://doi.org/10.1007/s10470-019-01437-7
 
مقالات ارائه‌شده در کنفرانس‌های بین‌المللی
  1. Sarang Kazeminia, Obalit Shino, Ehsan Haghigh, Khayrollah Hadidi, Abdollah Khoei,  “Improved Single-Stage Kickback-Rejected Comparator for High Speed and Low Noise Flash ADCs”, 21th European Conference on Circuit Theory and Design, 10.1109/ECCTD.2013.6662323, Dresden, Germany, 8-12 Sept. 2013, pp:1-4.

  2. Nahid Salehjoo, Sarang Kazeminia, Khayrollah Hadidi, “Producing Flat Supply Voltage Using A Temperature- Compensated BGR within LDO Regulator Loop”, 22nd Iranian Conference on Electrical Engineering, ICEE2014, Tehran, Iran, May2014, DOI:10.1109/IranianCEE.2014.6999521.

  3. Sarang Kazeminia, Sobhan Sofi Mowloodi, Khayrollah Hadidi, “Wide-Range 16-Phases DLL Based on Improved Dead- Zone Phase Detector and Reduced Gain Charge Pump”, 22nd Iranian Conference on Electrical Engineering, ICEE2014, Tehran, Iran, May 2014, DOI: 10.1109/IranianCEE.2014.6999518.

  4. Arash Hejazi, Sarang Kazeminia, Roozbeh Abdollahi, “A Digitally Assisted 20MHz-600MHz 16-Phase DLL Enhanced with Dynamic Gain Control Loop”, 22th European Conference on Circuit Theory and Design, 24-26 Aug 2015, Trondheim, Norway.  DOI:   10.1109/ECCTD.2015.7300073.

  5. Sarang Kazeminia and Obalit Shino, "Dual-loop enhanced-gain fast-response CMFB for open-loop RAs in high-resolution ADCs", 24th Iranian Conference on Electrical Engineering (ICEE 2016), May 2016, Shiraz, Iran, DOI: 10.1109/IranianCEE.2016.7585656.

  6. Sarang Kazeminia, Sina Mahdavi and Khayrollah Hadidi, "Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs", 23rd International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2016, Lodz, Poland, June 2016, DOI: 10.1109/MIXDES.2016.7529731.

  7. Sarang Kazeminia, Sina Mahdavi and Reza Gholamnejad, "Bulk controlled offset cancellation mechanism for single-stage latched comparator", 23rd International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2016, Lodz, Poland, June 2016, DOI: 10.1109/MIXDES.2016.7529726.

  8. Sarang Kazeminia and Sina Mahdavi, "A 800MS/s, 150µV input-referred offset single-stage latched comparator", 23rd International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2016, Lodz, Poland, June 2016, DOI: 10.1109/MIXDES.2016.7529714.

  9. Sarang Kazeminia and Arefeh Soltani, “Single-Stage Offset-Cancelled Latched Comparator Scheduled by Multi-Level Control on Reset Switch”, IEEE Asia Pacific Conference on Circuits and Systems, APCCAS2016, Jeju, Korea, October 2016.

  10. Sarang Kazeminia and Arefeh Soltani, “Digitally-Assisted Gain Calibration Strategy for Open-Loop Residue Amplifiers in Pipeline ADCs”, IEEE Asia Pacific Conference on Circuits and Systems, APCCAS2016, Jeju, Korea, October 2016.

  11. Arefeh Soltani, Roozbeh Abdollahi and Sarang Kazeminia, “Programmable Incrementing/Decrementing Binary Accumulator for High–Speed Calibration Loops”, IEEE International Conference on Electronics Circuits and Systems, ICECS2016, Monte Carlo, Monaco, December 2016.

  12. Ali Baradaran rezaeii, Sina mahdavi and Kazem Dadashi, “A novel method to design variable gain amplifier”; 1st international conference on engineering and applied sciences, Frankfurt, Germany, 10 march 2016.

  13. Ali Baradaran rezaeii and Abdollah Amini, “Statistic investigation and a novel design technique for improving the accuracy of the resistor string”; 3rd international conference on engineering and applied sciences, Frankfurt, Germany, 14 September 2016.

  14. Ali Baradaran rezaeii and Abdollah Amini, “A novel method to eliminate the mismatch effect of the current sources based on offset cancellation methods”; 3rd international conference on engineering and applied sciences, Frankfurt, Germany, 14 September 2016.

  15. Ali Baradaran rezaeii and Abdollah Amini, “A new high resolution calibration technique based on counter-DAC combination to eradicate mismatch effect of the current sources in 0.18µm CMOS”; 3rd international conference on engineering and applied sciences, Frankfurt, Germany, 14 September 2016.

  16. Ali Baradaran rezaeii, Kazem Dadashi and Sina mahdavi, “Gain-Bandwidth enhancement in Folded-Cascode Op-Amp”; 1st international conference on research achievements in electrical and computer engineering, Amirkabir university of technology, Tehran, Iran, 13 May 2016.

  17. Ali Baradaran rezaeii, Sina mahdavi, Kazem Dadashi and Tohid Moradi, “A novel feedback architecture in folded cascode amplifier for high-linearity and high-resolution applications qualified for different corners”; 1st international conference on research achievements in electrical and computer engineering, Amirkabir university of technology, Tehran, Iran, 13 May 2016.

  18. M. Ghasemzadeh, S. Mahdavi, A. Zokaei and K. Hadidi, "A new adaptive PLL to reduce the lock time in 0.18µm technology," 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 140-142.

  19. Mahdavi, Sina & Raheli, Farnaz & Moradkhani, Baran & Soltani, Arefeh. “A 41MHz 63dB and 1.22mW Variable Gain Amplifier in 0.18µm CMOS,” 3rd International Conference on Knowledge-Based Engineering and Innovation (KBEI-2016).

  20. Mahdavi, Sina & Noruzpur, Faeze & Alizadeh, Leyla & Jalilzadeh, Maryam & judy, Farahnaz. “A Novel and Reliable High accurate High linear Very low power and High-speed Continuous-time Common-Mode Feedback Circuit in 0.18µm CMOS,” 3rd International Conference on Knowledge-Based Engineering and Innovation (KBEI-2016).

  21. M. Ghasemzadeh, S. Mahdavi, A. Zokaei and K. Hadidi, "A new ultra high speed 5-2 compressor with a new structure," 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 151-154.

  22. Mahdavi, Sina & Moradi, Tohid & Baradaran Rezaeii, Ali. “A -8 to 42dB Wideband Dynamic Range and low power Variable Gain Amplifier in 0.18µm CMOS,” 2016 1st International Conference on New Research Achievements in Electrical and Computer Engineering.

  23. Sarang Kazeminia, Maryam Ghafoorzadeh and Faeze Noruzpour, “An Extendable Global Clock High-Speed Binray Counter Compatible to the FPGA CLBs”, 24th International Coonference on Mixed Design of Integrated Circuits and Systems, Bydgoszcz, Poland, June 2017.

  24. S. Mahdavi, R. Ebrahimi, A. Daneshdoust and A. Ebrahimi, "A 12bit 800MS/s and 1.37mW Digital to Analog Converter (DAC) based on novel R-C technique," 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI), Chennai, 2017, pp. 163-166.

  25. S. Mahdavi, F. Noruzpur, R. Ebrahimi and Z. Alizad, "Analysis simulation and comparison different types of the Sigma Delta ADC modulators based on ideal model system level and behavioral model using MATLAB," 2017 IEEE 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI), Tehran, 2017, pp. 0252-0259.

  26. S. Mahdavi, M. Jafarzadeh, M. Poreh and S. Ataei, "An ultra high-resolution low propagation delay time and low power with 1.25GS/s CMOS dynamic latched comparator for high-speed SAR ADCs in 180nm technology," 2017 IEEE 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI), Tehran, 2017, pp. 0260-0265.

  27. S. Mahdavi and E. Ghadimi, "A new 13-bit 100MS/s full differential successive approximation register analog to digital converter (SAR ADC) using a novel compound R-2R/C structure," 2017 IEEE 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI), Tehran, 2017, pp. 0237-0242.

  28. S. Mahdavi, B. Moradkhani and F. Noruzpur, "A −38 to 57dB 26.6MHz 1.96mW with 73.22dB SNDR variable gain amplifier in 0.18μm CMOS," 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI), Chennai, 2017, pp. 172-177.

  29. B. Rezaeii, F. Noruzpur and S. Mahdavi, "A novel APS pixel level rearrangement to increase the fill factor and SNR in 0.35μm CMOS technology," 2017 MIXDES – 24th International Conference "Mixed Design of Integrated Circuits and Systems, Bydgoszcz, 2017, pp. 205-210.

  30. S. Mahdavi, F. Noruzpur, E. Ghadimi and T. M. Khanshan, "A new fast rail-to-rail continuous-time common-mode feedback circuit," 2017 MIXDES – 24th International Conference "Mixed Design of Integrated Circuits and Systems, Bydgoszcz, 2017, pp. 387-391.

  31. Noruzpur, Faeze & Mahdavi, Sina & Poreh, Maryam & tayyeb ghasemi, shima. (2018). A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18µm Technology. 10.23919/MIXDES.2018.8443590.